1. Field
Provided is a method of patterning a block copolymer layer.
2. Description of the Related Art
Demands for lithography technology for forming a fine nano-sized pattern of a semiconductor memory or a logic circuit have increased in accordance with a decrease in a size of electronic devices including the semiconductor memory or the logic circuit, and an increase in a degree to which semiconductor devices have been integrated in electronic devices.
Conventional photolithography technology has difficulties in realizing a fine nano-sized pattern. In particular, a nano-pattern of less than or equal to about 20 nanometers (nm) are difficult to manufacture, due to a wavelength resolution limit. Accordingly, various methods based on new principles have been developed for fabricating nano-sized patterns. An example of such a new principle is a method of fabricating a nano-sized pattern by utilizing a self-assembled nano-structure of block copolymer.